J-BERT High-Performance Serial BERT / Jitter Tolerance Testing / 150 Mb/s to 7 Gb/s Pattern Generator / Includes Built-in CDR
From USD*20,300.88New Price 253,761.00 USD*
|Order as listed from Keysight Store on eBay:Buy Now Online20,300.88|
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The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forward clocked devices.
It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5Gb/s or 14.2 Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards, such as:
Accurate characterization is achieved with clean signals from the pattern generator, which features exceptionally low jitter and extremely fast transition times. Built-in and calibrated jitter source allow accurate jitter tolerance testing of receivers.
Test set-up is simplified significantly, because the J-BERT N4903B is designed to match serial bus standards optimally with its differential I/Os, variable voltage levels on most outputs, built-in jitter and ISI, pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic patterns.SER/FER analysis allows jitter tolerance testing of devices using retimed loopback. A second data output with independent pattern memory and PRBS can be used as aggressor channel for crosstalk tests, or when adding channels externally for OOB timing tests or emulation of 3-level signals or signal de-emphasis.
Faster test execution is possible with J-BERT’s automated jitter tolerance tests fast total jitter measurements.
The J-BERT N4903B is a long-term investment which is configurable for today’s test and budget requirements but also allows upgrades from the N4903A model, and later retrofit of all options and full speed when test needs change.
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